1. Field of the Invention
The present embodiments relate to wafer processing apparatus, and more particularly, apparatus, methods, for processing a wafer in a wafer processing apparatus.
2. Description of the Related Art
The manufacturing of integrated circuits includes immersing silicon substrates (wafers) containing regions of doped silicon in chemically-reactive plasmas, where the submicron device features (e.g., transistors, capacitors, etc.) are etched onto the surface. Once the first layer is manufactured, several insulating (dielectric) layers are built on top of the first layer, where holes, also referred to as vias, and trenches are etched into the material for placement of the conducting interconnectors.
Non-uniform etching can adversely impact wafer yield. Moreover, as the size of the critical dimension shrinks with each new generation of devices, and as wafer sizes increase to facilitate production of higher numbers of devices from the same wafer, non-uniformity requirements become ever more stringent. Thus, controlling non-uniformity is key to enabling more advanced technology nodes to be produced in a cost-effective manner.
It is in this context that embodiments of the invention arise.